A 5Gbit/s/pin transceiver for high-speed memory interfaces is implemented in a 0.18 mu m CMOS process. In general, memory interfaces use single-ended signalling with a reference signal because the chip cost is closely related to the number of pins. However, as the data rate increases, reference voltage noise and simultaneous switching noise reduce voltage and timing margin of receiver input signals. Pseudo-differential signalling (PDS) is used to solve the problems, however a previous receiver using PDS is sensitive to core power noise because the receiver uses three-level signals with reduced noise margin. The three-level differential buffer (TLDB) which is robust to core power noise is proposed and the noise margin of the TLDB outputs is larger than that of outputs of a previous PDS receiver.