Three-stage clos-network switch architecture with buffered center stage for multi-class traffic

Abstract

Memory-space-memory (MSM) arrangement is a popular architecture to implement three-stage Clos network switches with distributed arbitration. The scalability of this architecture, however, is limited by the round-trip communication delay between the first and the second stages. Virtual output queue (VOQ) cannot completely remove the blocking in the buffered modules under multi-class traffic conditions. In this paper, we propose a competition-free memory-memory-memory $(CFM^3)$ switch which is a three-stage Clos network switch with buffered center stage. The $CFM^3$ deploys buffered modules in all stages to simplify communication between stages. To reduce the blocking, each module is equipped with a set of buffers fully separated according to the destinations, classes of packets and the input ports of the module. Despite the buffered center stage, $CFM^3$ is free from reordering problem due to simple control mechanism. Memory overhead to implement the $CFM^3$ switch is negligible. Simulation result shows that the delay of the proposed $CFM^3$ switch closely approaches that of the ideal Output Queued switch under multi-class traffic conditions when strict priority policy popularly used for class-based switch is deployed. $CFM^3$ achieves 100% throughput under uniformly distributed four-class traffic with strict priority policy while traditional MSM switch achieves only 77% throughput.