A study on coining processes of solder bumps on organic substrates

Abstract

Solder flip chip bumping and subsequent coining processes on printed circuit board (PCB) were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation; 1) region of elastic deformation; 2) region of linearly increase of applied loads; 3) region of rapidly increase of applied loads. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Lower coining loads were needed to prevent potentail substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying coining loads. It was found that coining process temperature had more significant effect to reduce applied coining loads during the coining process.