Coupling-Aware Minimum Delay Optimization for Domino Logic Circuits

Abstract

Minimum delay associated with the hold time requirement is a concern to circuit designers, since race-through hazards are inherent to any multiple clock organisation or clock distribution tree irrespective of clock frequency. The monotonic property of domino logic aggravates the minimum-delay path failure through coupling-induced speedup. To tackle the minimum-delay problem for domino logic, we propose a minimum-delay optimisation algorithm considering coupling effects. Experimental results indicate that our algorithm yields a significant increase of minimum-delay without incurring maximum-delay violation.