DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ki-Wook Kim | ko |
dc.contributor.author | Seong-Ook Jung | ko |
dc.contributor.author | Taewhan Kim | ko |
dc.contributor.author | Sung-Mo Kang | ko |
dc.date.accessioned | 2013-03-03T18:03:39Z | - |
dc.date.available | 2013-03-03T18:03:39Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2001-06 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v.37, no.13, pp.813 - 814 | - |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/79818 | - |
dc.description.abstract | Minimum delay associated with the hold time requirement is a concern to circuit designers, since race-through hazards are inherent to any multiple clock organisation or clock distribution tree irrespective of clock frequency. The monotonic property of domino logic aggravates the minimum-delay path failure through coupling-induced speedup. To tackle the minimum-delay problem for domino logic, we propose a minimum-delay optimisation algorithm considering coupling effects. Experimental results indicate that our algorithm yields a significant increase of minimum-delay without incurring maximum-delay violation. | - |
dc.language | English | - |
dc.publisher | Inst Engineering Technology-Iet | - |
dc.title | Coupling-Aware Minimum Delay Optimization for Domino Logic Circuits | - |
dc.type | Article | - |
dc.identifier.wosid | 000169697100007 | - |
dc.identifier.scopusid | 2-s2.0-0035927563 | - |
dc.type.rims | ART | - |
dc.citation.volume | 37 | - |
dc.citation.issue | 13 | - |
dc.citation.beginningpage | 813 | - |
dc.citation.endingpage | 814 | - |
dc.citation.publicationname | ELECTRONICS LETTERS | - |
dc.identifier.doi | 10.1049/el:20010554 | - |
dc.contributor.localauthor | Taewhan Kim | - |
dc.contributor.nonIdAuthor | Ki-Wook Kim | - |
dc.contributor.nonIdAuthor | Seong-Ook Jung | - |
dc.contributor.nonIdAuthor | Sung-Mo Kang | - |
dc.type.journalArticle | Article | - |
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