A novel hierarchical-search block matching algorithm and VLSI architecture considering the spatial complexity of the macroblock

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In this paper, we propose a novel hierarchical-search block matching algorithm for motion estimation, which adaptively selects an initial search level based on the spatial complexity of a matching block. It relies on a simple computation of pixel intensity variation in the current macroblock. We demonstrate its effectiveness in two aspects: the performance and the computational cost. A hardware architecture and a VLSI realization of this algorithm with half-pel motion estimation and motion compensation are also presented. The proposed algorithm greatly reduces the computations required in the existing hierarchical-search block matching algorithms while achieves virtually identical performance to them.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
1998-05
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, v.44, no.2, pp.337 - 342

ISSN
0098-3063
URI
http://hdl.handle.net/10203/78136
Appears in Collection
RIMS Journal Papers
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