A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system

Cited 19 time in webofscience Cited 21 time in scopus
  • Hit : 377
  • Download : 0
A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at V-cc = 3.3 V and T = 25 degrees C. The circuit features are: 1) a bidirectional data strobing scheme to eliminate the clock-related skews of I/O data in a multimodule system, 2) a low-power delay-locked loop having a wide range of locking frequency (40-160 MHz) with fast access time and minimal variations, and 3) a twisted data bussing architecture with minimized loading difference between I/O data paths and small chip-size overhead associated with the 2-bit prefetch operation.
Publisher
IEEE-Inst Electrical Electronics Engineers Inc
Issue Date
1998-11
Language
English
Article Type
Article
Keywords

DELAY

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.33, no.11, pp.1703 - 1710

ISSN
0018-9200
DOI
10.1109/4.726563
URI
http://hdl.handle.net/10203/67713
Appears in Collection
RIMS Journal Papers
Files in This Item
There are no files associated with this item.
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡ Click to see webofscience_button
⊙ Cited 19 items in WoS Click to see citing articles in records_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0