A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system

Abstract

A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at V-cc = 3.3 V and T = 25 degrees C. The circuit features are: 1) a bidirectional data strobing scheme to eliminate the clock-related skews of I/O data in a multimodule system, 2) a low-power delay-locked loop having a wide range of locking frequency (40-160 MHz) with fast access time and minimal variations, and 3) a twisted data bussing architecture with minimized loading difference between I/O data paths and small chip-size overhead associated with the 2-bit prefetch operation.