COFACTOR PACKING ALGORITHM FOR LOOKUP-TABLE BASED FIELD-PROGRAMMABLE GATE ARRAYS

Abstract

The authors present a new technology mapping algorithm for an LUT-based FPGA. Decomposition of a Boolean network is formulated as an algebraic cofactoring, and the technology mapping is performed by cofactor packing. Experimental results show that the proposed method decomposes infeasible nodes in a shorter CPU time with more than 10% reduced number of nodes compared with previous decomposition methods.