COFACTOR PACKING ALGORITHM FOR LOOKUP-TABLE BASED FIELD-PROGRAMMABLE GATE ARRAYS
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | PARK, SS | ko |
| dc.contributor.author | LEE, YH | ko |
| dc.contributor.author | HWANG, SH | ko |
| dc.contributor.author | Kyung, Chong-Min | ko |
| dc.date.accessioned | 2013-02-25T01:20:36Z | - |
| dc.date.available | 2013-02-25T01:20:36Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 1994-07 | - |
| dc.identifier.citation | ELECTRONICS LETTERS, v.30, no.15, pp.1207 - 1209 | - |
| dc.identifier.issn | 0013-5194 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/58717 | - |
| dc.description.abstract | The authors present a new technology mapping algorithm for an LUT-based FPGA. Decomposition of a Boolean network is formulated as an algebraic cofactoring, and the technology mapping is performed by cofactor packing. Experimental results show that the proposed method decomposes infeasible nodes in a shorter CPU time with more than 10% reduced number of nodes compared with previous decomposition methods. | - |
| dc.language | English | - |
| dc.publisher | IEE-INST ELEC ENG | - |
| dc.title | COFACTOR PACKING ALGORITHM FOR LOOKUP-TABLE BASED FIELD-PROGRAMMABLE GATE ARRAYS | - |
| dc.type | Article | - |
| dc.identifier.wosid | A1994PA87100012 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 30 | - |
| dc.citation.issue | 15 | - |
| dc.citation.beginningpage | 1207 | - |
| dc.citation.endingpage | 1209 | - |
| dc.citation.publicationname | ELECTRONICS LETTERS | - |
| dc.contributor.localauthor | HWANG, SH | - |
| dc.contributor.localauthor | Kyung, Chong-Min | - |
| dc.contributor.nonIdAuthor | PARK, SS | - |
| dc.contributor.nonIdAuthor | LEE, YH | - |
| dc.type.journalArticle | Article | - |
| dc.subject.keywordAuthor | PROGRAMMABLE LOGIC ARRAYS | - |
| dc.subject.keywordAuthor | ALGORITHM THEORY | - |
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