Search
Results 1-10 of 30 (Search time: 0.005 seconds).
| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| Microwave frequency model of water level package and increased loading effect on rambus memory module Lee, J.; Choi, B.; Ahn, S.; Ryu, W.; Kim, J.M.; Choi, K.S.; Hong, J.-K.; Chun, H.-S.; Kim, Joungho, 51st Electronic Components and Technology Conference, pp.128 - 132, 2001-05-29 | |
| The improvement of Signal Integrity (SI) according to the location of via in the vicinity of a slot in the reference plane Kim, T.H.; Lee, J.; Kim, H.; Jun, P.J.; Kim, Joungho, 6th IEEE Workshop on Signal Propagation on Interconnects, SPI, pp.185 - 188, IEEE, 2002-05-12 | |
| Slot transmission line model of interconnections crossing split power/ground plane on high-speed multi-layer board Kim, Joungho; Kim, H.; Jeong, Y.; Lee, J.; Kim, J., 6th IEEE Workshop on Signal Propagation on Interconnects, SPI, pp.23 - 26, 2002-05-12 | |
| Compensation of BSD and device input capacitance by using embedded inductor on PCB substrate for 3 Gbps SerDes applications Ahn, S.; Baek, S.; Lee, J.; Kim, Joungho, 2004 International Symposium on Electromagnetic Compatibility, EMC 2004, v.2, pp.499 - 504, 2004-08-09 | |
| Reduction of multilayer PCB edge radiation excited by through-hole signal via with De-Cap Fence Kim, Joungho; Pak, J. S.; Lee, J., 2003 Asia-Pacific Microwave Conference, pp.870 - 873, 2003 | |
| Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer Yoon, K.; Kim, G.; Lee, W.; Song, T.; Lee, J.; Lee, H.; Park, K.; Kim, Joungho, 2009 11th Electronic Packaging Technology Conference, EPTC 2009, pp.702 - 706, 2009-12-09 | |
| Impact of partial EBG PDN on PI, SI and lumped model-based correlation Lee, J.; Lee, H.; Park, K.; Chung, B.; Kim, J.; Kim, Joungho, 2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008, pp.168 - 171, 2008-05-19 | |
| Modeling and analysis of die-to-die vertical coupling in 3-D IC Lee, S.; Kim, G.; Kim, J.; Song, T.; Lee, J.; Lee, H.; Park, K.; Kim, Joungho, 2009 11th Electronic Packaging Technology Conference, EPTC 2009, pp.707 - 711, 2009-12-09 | |
| High frequency electrical circuit model of chip-to-chip vertical via iterconnection for 3-D chip stacking package Ryu, C.; Chung, D.; Lee, J.; Lee, K.; Oh, T.; Kim, Joungho, 14th Topical Meeting on Electrical Performance of Electronic Packaging 2005, v.2005, pp.151 - 154, 2005-10-24 | |
| Effect of decoupling capacitor on signal integrity in applications with reference plane change Lee, J.; Lu, A.C.W.; Fan, W.; Wai, L.L.; Kim, Joungho, 53rd Electronic Components and Technology Conference, 2003, pp.1283 - 1288, IEEE, 2003-05-27 |