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Showing results 11 to 13 of 13

11
Implementation of low jitter clock distribution using chip-package hybrid interconnection

Ryu, C.; Chung, D.; Bae, K.; Yu, J.; Kim, Joungho, IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging, pp.291 - 294, IEEE, 2004-10-25

12
Jitter suppressed on-chip clock distribution using package plane cavity resonance

Lee, W.; Ryu, C.; Park, J.; Kim, Joungho, 2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008, pp.427 - 430, IEEE, 2008-05-19

13
Wideband low power distribution network impedance of high chip density package using 3-D stacked through silicon vias

Pak, J.S.; Ryu, C.; Kim, J.; Shim, Y.; Kim, G.; Kim, Joungho, 2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, APEMC 2008, pp.351 - 354, IEEE, 2008-05-19

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