We describe parallel processes for nanometer pattern generation on a wafer scale with resolution comparable to the best electron beam lithography. Sub-10 nm linewidth is defined by a sacrificial ultrathin film deposited by low pressure chemical vapor deposition (LPCVD), in a process similar to formation of gate sidewall spacers in CMOS processing. We further demonstrate a method called iterative spacer lithography (ISL), in which the process is repeated multiple times with alternating materials in order to multiply the pattern density. Silicon structures with sub-10 nm width fabricated by this process were used as a mold in nanoimprint lithography and lift-off patterning of sub-30 nm platinum nanowires for use in experiments on chemical catalysis. We also demonstrate a similar process called reversed spacer lithography (RSL) to form sub-10 nm fluid channels in poly-Si. This nanogap fluid channel device was used for label-free detection of DNA hybridization based on electrical sensing of dielectric changes in the gap. (C) 2003 American Vacuum Society.