Analog circuit design automation framework with device sizing algorithm

Abstract

Recently, numerous analog and mixed-signal (AMS) integrated circuits (ICs) for various applications, such as System-on-Chip (SoC) or Internet-of-Things (IoT) are in high demand. However, the AMS IC design process heavily relies on the designer's skill and consumes a lot of time due to repetitive design modification. As the productivity of a new IC design cannot satisfy the increasing demand, closed-loop design automation with layout generation and optimization is required to accelerate the design time. In this study, an analog circuit design automation framework with a device sizing algorithm is proposed. The design loop conducts the required design procedures such as layout generation, parasitic extraction, and simulation. Meanwhile, the optimization algorithm determines the device parameters to satisfy the given target specifications. By combining the optimization algorithm with the design loop, closed-loop design automation without human intervention can be achieved. As circuit simulations are costly and derivatives with respect to input parameters cannot be obtained, constrained Bayesian optimization (CBO) is utilized for the optimization algorithm. As design examples, comparators are designed automatically with minimized power consumption and given target specifications. With this automatically designed comparator, SAR ADC is implemented.