High speed low power pipelined SAR ADC with current-mode back-end processing

Abstract

Recently, analog-to-digital converters (ADC) using current-mode processing for various applications have been studied. This thesis proposes a novel current-mode processing technique for high-speed and low-power ADC.At first, this paper introduces a current-mode residue processing technique in a pipelined-SAR analog-to-digital converter (ADC), which extends the operation speed of a single-channel ADC utilizing low-impedance-based signaling. A 10-bit pipelined-SAR ADC with featured building blocks such as a degenerated gm-cell as an open-loop residue amplifier, a switched-current mirror for sample-and-hold (S/H) function, and a split current DAC for current-domain SAR conversion achieves a 500-MS/s conversion-rate under a 1.0-V supply. With background inter-stage mismatch calibration, a prototype ADC fabricated in a 28-nm CMOS process achieves 56.6-dB SNDR at a Nyquist input, resulting in a Walden FoM of a 21.7 fJ/conversion-step.Next, This paper introduces a voltage-current-time (V-I-T) domain 3-stage pipelined analog-to-digital converter (ADC) that exploits the speed of both the current-domain and the time-domain processing. An open-loop current-to-time pipelining with a calibration-free time-to-digital converter (TDC) utilizing a full-scale-matched current-to-time converter (ITC) enhances the conversion speed of a time-domain back-end ADC while ensuring the robustness to PVT variations. With voltage-to-current stage background calibration, a prototype 12-bit 250-MS/s ADC fabricated in a 28-nm CMOS process achieves an SNDR of 61.5 dB at a Nyquist input, resulting in a 22.2fJ/conversion-step Walden FoM under a 1.0V supply.