DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Ryu, Seung-Tak | - |
dc.contributor.advisor | 류승탁 | - |
dc.contributor.author | Moon, Kyoung-Jun | - |
dc.date.accessioned | 2021-05-12T19:42:08Z | - |
dc.date.available | 2021-05-12T19:42:08Z | - |
dc.date.issued | 2019 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=913341&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/284266 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2019.8,[iv, 50 p. :] | - |
dc.description.abstract | Recently, analog-to-digital converters (ADC) using current-mode processing for various applications have been studied. This thesis proposes a novel current-mode processing technique for high-speed and low-power ADC.At first, this paper introduces a current-mode residue processing technique in a pipelined-SAR analog-to-digital converter (ADC), which extends the operation speed of a single-channel ADC utilizing low-impedance-based signaling. A 10-bit pipelined-SAR ADC with featured building blocks such as a degenerated gm-cell as an open-loop residue amplifier, a switched-current mirror for sample-and-hold (S/H) function, and a split current DAC for current-domain SAR conversion achieves a 500-MS/s conversion-rate under a 1.0-V supply. With background inter-stage mismatch calibration, a prototype ADC fabricated in a 28-nm CMOS process achieves 56.6-dB SNDR at a Nyquist input, resulting in a Walden FoM of a 21.7 fJ/conversion-step.Next, This paper introduces a voltage-current-time (V-I-T) domain 3-stage pipelined analog-to-digital converter (ADC) that exploits the speed of both the current-domain and the time-domain processing. An open-loop current-to-time pipelining with a calibration-free time-to-digital converter (TDC) utilizing a full-scale-matched current-to-time converter (ITC) enhances the conversion speed of a time-domain back-end ADC while ensuring the robustness to PVT variations. With voltage-to-current stage background calibration, a prototype 12-bit 250-MS/s ADC fabricated in a 28-nm CMOS process achieves an SNDR of 61.5 dB at a Nyquist input, resulting in a 22.2fJ/conversion-step Walden FoM under a 1.0V supply. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Analog-to-digital converter (ADC)▼apipelined-SAR▼acurrent-mode residue processing▼acurrent-domain▼agm-cell▼aopen-loop amplifier▼asplit current DAC▼atime-domain▼avoltage-current-time pipelined ADC▼acalibration-free current-to-time converter▼atime-to-digital converter(TDC) | - |
dc.subject | 아날로그-디지털 변환기▼a파이프라인 축차 비교▼a전류모드 잔류전압 프로세싱▼a전류 도메인▼a트랜스컨덕턴스 셀▼a개루프 증폭기▼a스플릿 전류 디지털-아날로그 변환기▼a시간 도메인▼a전압-전류-시간 파이프라인 변환기▼a캘리브레이션 프리 전류-시간 변환기▼a시간-디지털 변환기 | - |
dc.title | High speed low power pipelined SAR ADC with current-mode back-end processing | - |
dc.title.alternative | 전류모드 프로세싱을 이용한 고속 저전력 파이프라인 축차 비교형 아날로그-디지털 변환기 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
dc.contributor.alternativeauthor | 문경준 | - |
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