A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells

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This paper presents a PVT-robust, low-jitter, injection-locked clock multiplier with the frequency resolution of one tenth of the reference frequency, using a DLL-based PVT-calibrator. As the key idea, the ring-VCO and the DLL consist of identical delay cells and share the control voltage. Since the DLL continually corrects the delay of the unit delay cells, the degradation of jitter due to the drift of the free-running VCO frequency can be prevented. The RMS-jitter was 448 fs, and its variation with temperature was regulated to be less than ± 4%.
Publisher
Institute of Electrical and Electronics Engineers Inc.
Issue Date
2015-06-01
Language
English
Citation

29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015, pp.C142 - C143

DOI
10.1109/VLSIC.2015.7231356
URI
http://hdl.handle.net/10203/269664
Appears in Collection
EE-Conference Papers(학술회의논문)
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