DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Mina | ko |
dc.contributor.author | Choi, Seojin | ko |
dc.contributor.author | Choi, Jaehyouk | ko |
dc.date.accessioned | 2019-12-13T13:27:19Z | - |
dc.date.available | 2019-12-13T13:27:19Z | - |
dc.date.created | 2019-11-19 | - |
dc.date.created | 2019-11-19 | - |
dc.date.created | 2019-11-19 | - |
dc.date.issued | 2015-06-01 | - |
dc.identifier.citation | 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015, pp.C142 - C143 | - |
dc.identifier.uri | http://hdl.handle.net/10203/269664 | - |
dc.description.abstract | This paper presents a PVT-robust, low-jitter, injection-locked clock multiplier with the frequency resolution of one tenth of the reference frequency, using a DLL-based PVT-calibrator. As the key idea, the ring-VCO and the DLL consist of identical delay cells and share the control voltage. Since the DLL continually corrects the delay of the unit delay cells, the degradation of jitter due to the drift of the free-running VCO frequency can be prevented. The RMS-jitter was 448 fs, and its variation with temperature was regulated to be less than ± 4%. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells | - |
dc.type | Conference | - |
dc.identifier.wosid | 000370961400054 | - |
dc.identifier.scopusid | 2-s2.0-84957885084 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | C142 | - |
dc.citation.endingpage | C143 | - |
dc.citation.publicationname | 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 | - |
dc.identifier.conferencecountry | JA | - |
dc.identifier.conferencelocation | Kyoto | - |
dc.identifier.doi | 10.1109/VLSIC.2015.7231356 | - |
dc.contributor.localauthor | Choi, Jaehyouk | - |
dc.contributor.nonIdAuthor | Kim, Mina | - |
dc.contributor.nonIdAuthor | Choi, Seojin | - |
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