An external capacitor-less ultra low-dropout (LDO) regulator that can continue to provide high power-supply rejection (PSR) over a wide range of the load current is proposed. Using the loop-gain stabilizer (LGS) to fix the dc level of the output voltage of the error amplifier to the optimal value, the LDO can keep maximizing the unity-gain frequency, while the load current changes widely up to 200 mA. Despite the multiple poles in the regulating loop, the stability can easily be obtained due to an intrinsic left-half plane zero, generated by the auxiliary path of the LGS. The proposed LDO was fabricated in a 40-nm CMOS process, and it had an input voltage of 1.1 V. When the dropout voltage was 0.1 V and the load current was 200 mA, the measured PSRs were -60 and -35 dB at 1 and 10 MHz, respectively. Due to the LGS, the dc loop gain was maintained to be high, resulting in good load and line regulations of 19 mu V/mA and 0.75 mV/V, respectively. While the total current consumption of the LDO was 275 mu A, the LGS consumed only 7 mu A. The area was 0.008 mm(2) with 4-pF on-chip capacitance for compensation.