Double-gated ultra-thin-body GaAs-on-insulator p-FETs on Si

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We demonstrated ultra-thin-body (UTB) junctionless (JL) p-type field-effect transistors (pFETs) on Si using GaAs channels. Wafer bonding and epitaxial lift-off techniques were employed to fabricate the UTB p-GaAs-on-insulator on a Si template. Subsequently, we evaluated the JL FETs having different p-GaAs channel thicknesses considering both maximum depletion width and doping concentration for high performance. Furthermore, by introducing a double-gate operation, we more effectively controlled threshold voltage and attained an even higher I-ON/I-OFF of > 10(6), as well as a low subthreshold swing value of 300 mV/dec. (c) 2018 Author(s).
Publisher
AMER INST PHYSICS
Issue Date
2018-01
Language
English
Article Type
Article
Citation

APL MATERIALS, v.6, no.1

ISSN
2166-532X
DOI
10.1063/1.5000532
URI
http://hdl.handle.net/10203/250255
Appears in Collection
RIMS Journal Papers
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