A 0.65V, 11.2Gb/s Power Noise Tolerant Source-synchronous injection-locked Receiver with Direct DTLB DFE

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This brief presents a 0.65V power noise tolerant source-synchronous injection-locked receiver with 13.4dB channel loss compensation. To meet the 1UI timing constraint for the decision feedback equalizer in low supply, SR latches are removed in the feedback path, and return to zero recovered data is used for equalization. Additionally, a power noise sensitivity of low supply is relieved by current and PMOS body bias control techniques of an oscillator. The test core fabricated in 65nm CMOS process achieves 11.2Gb/s with 0.303pJ/bit FOM compensating 13.4dB channel loss at 5.6GHz.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-11
Language
English
Article Type
Article
Keywords

PJ/BIT; CMOS

Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.11, pp.1564 - 1568

ISSN
1549-7747
DOI
10.1109/TCSII.2017.2764122
URI
http://hdl.handle.net/10203/246511
Appears in Collection
EE-Journal Papers(저널논문)
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