A 0.65V, 11.2Gb/s Power Noise Tolerant Source-synchronous injection-locked Receiver with Direct DTLB DFE

Abstract

This brief presents a 0.65V power noise tolerant source-synchronous injection-locked receiver with 13.4dB channel loss compensation. To meet the 1UI timing constraint for the decision feedback equalizer in low supply, SR latches are removed in the feedback path, and return to zero recovered data is used for equalization. Additionally, a power noise sensitivity of low supply is relieved by current and PMOS body bias control techniques of an oscillator. The test core fabricated in 65nm CMOS process achieves 11.2Gb/s with 0.303pJ/bit FOM compensating 13.4dB channel loss at 5.6GHz.