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Kim, Lee-Sup (김이섭)
교수, School of Electrical Engineering(전기및전자공학부)
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    NO Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date)
    1
    A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE with Non-Time-Overlapping Data Generation for 4:1 CMOS Clockless Multiplexer

    Lee, Daewoong; Lee, Dongil; Kim, Yong-Hun; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.67, no.1, pp.67 - 71, 2020-01

    2
    An Energy-Efficient Deep Convolutional Neural Network Inference Processor With Enhanced Output Stationary Dataflow in 65-nm CMOS

    Sim, Jaehyeong; Lee, Somin; Kim, Lee-Supresearcher, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.28, no.1, pp.87 - 100, 2020-01

    3
    A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS

    Jung, Chongsoo; Lee, Dongil; Kim, Yong-Hun; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.12, pp.1972 - 1976, 2019-12

    4
    DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells

    Choi, Jungwhan; Jang, Jaemin; Kim, Lee-Supresearcher, IEEE TRANSACTIONS ON COMPUTERS, v.68, no.12, pp.1741 - 1754, 2019-12

    5
    Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory

    Jang, Jaemin; Shin, Wongyu; Choi, Jungwhan; et al, IEEE TRANSACTIONS ON COMPUTERS, v.68, no.5, pp.752 - 764, 2019-05

    6
    A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control

    Lee, Daewoong; Lee, Dongil; Kim, Yong-Hun; et al, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.27, no.3, pp.724 - 728, 2019-03

    7
    A 0.9-V 12-Gb/s 2-FIR Tap Direct DFE with Feedback-Signal Common-Mode-Control

    Lee, Daewoong; Lee, Dongil; Kim, Yong-Hun; et al, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.27, no.3, pp.724 - 728, 2019-03

    8
    A 10 Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption with Direct Feedback Method

    Kim, Yong-Hun; Lee, Dongil; Lee, Daewoong; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.11, pp.1539 - 1543, 2018-11

    9
    A 0.65V, 11.2Gb/s Power Noise Tolerant Source-synchronous injection-locked Receiver with Direct DTLB DFE

    Lee, Dongil; Kim, Yong-Hun; Lee, Daewoong; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.11, pp.1564 - 1568, 2018-11

    10
    Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs

    Seol, Hoseok; Shin, Wongyu; Jang, Jaemin; et al, IEEE TRANSACTIONS ON COMPUTERS, v.67, no.10, pp.1403 - 1415, 2018-10

    11
    Energy-Efficient Design of Processing Element for Convolutional Neural Network

    Choi, Yeongjae; Bae, Dongmyung; Sim, Jaehyeong; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.11, pp.1332 - 1336, 2017-11

    12
    In-DRAM Data Initialization

    Seol, Hoseok; Shin, Wongyu; Jang, Jaemin; et al, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.11, pp.3251 - 3254, 2017-11

    13
    Rank-Level Parallelism in DRAM

    Shin, Wongyu; Jang, Jaemin; Choi, Jungwhan; et al, IEEE TRANSACTIONS ON COMPUTERS, v.66, no.7, pp.1274 - 1280, 2017-07

    14
    An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface

    Kim, Yonghun; Lee, Taeho; Jeon, Hyun-Kyu; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.64, no.4, pp.823 - 835, 2017-04

    15
    Refresh-Aware Write Recovery Memory Controller

    Jang, Jaemin; Shin, Wongyu; Choi, Jungwhan; et al, IEEE TRANSACTIONS ON COMPUTERS, v.66, no.4, pp.688 - 701, 2017-04

    16
    A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network

    Lee, Taeho; Kim, Yong Hun; Kim, Lee-Supresearcher, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.1, pp.380 - 384, 2017-01

    17
    A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network

    Lee, Taeho; Kim, Yong Hun; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.1, pp.380 - 384, 2017-01

    18
    A Vision Processor With a Unified Interest-Point Detection and Matching Hardware for Accelerating a Stereo-Matching Algorithm

    Park, Jun-Seok; Kim, Hyo-Eun; Kim, Hong-Yun; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, v.26, no.12, pp.2328 - 2343, 2016-12

    19
    DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing

    Shin, Wongyu; Choi, Jungwhan; Jang, Jaemin; et al, IEEE TRANSACTIONS ON COMPUTERS, v.65, no.10, pp.3027 - 3040, 2016-10

    20
    A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector

    Lee, Dongil; Lee, Taeho; Kim, Young-Ju; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.63, no.8, pp.733 - 737, 2016-08

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