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Kim, Lee-Sup (김이섭)
교수, School of Electrical Engineering(전기및전자공학부)
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    NO Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date)
    1
    A Framework for Accelerating Transformer-based Language Model on ReRAM-based Architecture

    Kang, Myeonggu; Shin, Hyein; Kim, Lee-Supresearcher, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.41, no.9, pp.3026 - 3039, 2022-09

    2
    S-FLASH: A NAND Flash-based Deep Neural Network Accelerator Exploiting Bit-level Sparsity

    Kang, Myeonggu; Kim, Hyeonuk; Shin, Hyein; et al, IEEE TRANSACTIONS ON COMPUTERS, v.71, no.6, pp.1291 - 1304, 2022-06

    3
    A Deep Neural Network Training Architecture with Inference-aware Heterogeneous Data-type

    Choi, Seungkyu; Shin, Jaekang; Kim, Lee-Supresearcher, IEEE TRANSACTIONS ON COMPUTERS, v.71, no.5, pp.1216 - 1229, 2022-05

    4
    Rare Computing: Removing Redundant Multiplications from Sparse and Repetitive Data in Deep Neural Networks

    Park, Kangkyu; Choi, Seungkyu; Choi, Yeongjae; et al, IEEE TRANSACTIONS ON COMPUTERS, v.71, no.4, pp.795 - 808, 2022-04

    5
    Quantization-Error-Robust Deep Neural Network for Embedded Accelerators

    Jung, Youngbeom; Kim, Hyeonuk; Choi, Yeongjae; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.69, no.2, pp.609 - 613, 2022-02

    6
    Amnesiac DRAM: A Proactive Defense Mechanism Against Cold Boot Attacks

    Seol, Hoseok; Kim, Minhye; Kim, Taesoo; et al, IEEE TRANSACTIONS ON COMPUTERS, v.70, no.4, pp.539 - 551, 2021-04

    7
    CREMON: Cryptography Embedded on the Convolutional Neural Network Accelerator

    Choi, Yeongjae; Sim, Jaehyeong; Kim, Lee-Supresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.67, no.12, pp.3337 - 3341, 2020-12

    8
    An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In-Situ Personalization on Smart Devices

    Choi, Seungkyu; Sim, Jaehyeong; Kang, Myeonggu; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.55, no.10, pp.2691 - 2702, 2020-10

    9
    An Energy-Efficient Deep Convolutional Neural Network Inference Processor With Enhanced Output Stationary Dataflow in 65-nm CMOS

    Sim, Jaehyeong; Lee, Somin; Kim, Lee-Supresearcher, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.28, no.1, pp.87 - 100, 2020-01

    10
    A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE with Non-Time-Overlapping Data Generation for 4:1 CMOS Clockless Multiplexer

    Lee, Daewoong; Lee, Dongil; Kim, Yong-Hun; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.67, no.1, pp.67 - 71, 2020-01

    11
    A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS

    Jung, Chongsoo; Lee, Dongil; Kim, Yong-Hun; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.12, pp.1972 - 1976, 2019-12

    12
    DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells

    Choi, Jungwhan; Jang, Jaemin; Kim, Lee-Supresearcher, IEEE TRANSACTIONS ON COMPUTERS, v.68, no.12, pp.1741 - 1754, 2019-12

    13
    Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory

    Jang, Jaemin; Shin, Wongyu; Choi, Jungwhan; et al, IEEE TRANSACTIONS ON COMPUTERS, v.68, no.5, pp.752 - 764, 2019-05

    14
    A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control

    Lee, Daewoong; Lee, Dongil; Kim, Yong-Hun; et al, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.27, no.3, pp.724 - 728, 2019-03

    15
    A 10 Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption with Direct Feedback Method

    Kim, Yong-Hun; Lee, Dongil; Lee, Daewoong; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.11, pp.1539 - 1543, 2018-11

    16
    A 0.65V, 11.2Gb/s Power Noise Tolerant Source-synchronous injection-locked Receiver with Direct DTLB DFE

    Lee, Dongil; Kim, Yong-Hun; Lee, Daewoong; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.11, pp.1564 - 1568, 2018-11

    17
    Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs

    Seol, Hoseok; Shin, Wongyu; Jang, Jaemin; et al, IEEE TRANSACTIONS ON COMPUTERS, v.67, no.10, pp.1403 - 1415, 2018-10

    18
    In-DRAM Data Initialization

    Seol, Hoseok; Shin, Wongyu; Jang, Jaemin; et al, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.11, pp.3251 - 3254, 2017-11

    19
    Energy-Efficient Design of Processing Element for Convolutional Neural Network

    Choi, Yeongjae; Bae, Dongmyung; Sim, Jaehyeong; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.11, pp.1332 - 1336, 2017-11

    20
    Rank-Level Parallelism in DRAM

    Shin, Wongyu; Jang, Jaemin; Choi, Jungwhan; et al, IEEE TRANSACTIONS ON COMPUTERS, v.66, no.7, pp.1274 - 1280, 2017-07

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