Negative capacitance logic device, clock generator including the same and method of operating clock generator네가티브 커패시턴스 논리 장치, 작동 클록 제너레이터의 동일한 것 및 방법을 포함해 클럭 발생 장치
A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node.