DC Field | Value | Language |
---|---|---|
dc.contributor.author | 신민철 | ko |
dc.contributor.author | 이재현 | ko |
dc.contributor.author | 강두형 | ko |
dc.contributor.author | 서준범 | ko |
dc.contributor.author | 정우진 | ko |
dc.date.accessioned | 2017-12-20T02:11:38Z | - |
dc.date.available | 2017-12-20T02:11:38Z | - |
dc.date.issued | 2016-11-01 | - |
dc.identifier.uri | http://hdl.handle.net/10203/230363 | - |
dc.description.abstract | A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node. | - |
dc.title | Negative capacitance logic device, clock generator including the same and method of operating clock generator | - |
dc.title.alternative | 네가티브 커패시턴스 논리 장치, 작동 클록 제너레이터의 동일한 것 및 방법을 포함해 클럭 발생 장치 | - |
dc.type | Patent | - |
dc.type.rims | PAT | - |
dc.contributor.localauthor | 신민철 | - |
dc.contributor.nonIdAuthor | 이재현 | - |
dc.contributor.nonIdAuthor | 강두형 | - |
dc.contributor.nonIdAuthor | 서준범 | - |
dc.contributor.nonIdAuthor | 정우진 | - |
dc.contributor.assignee | 한국과학기술원 | - |
dc.identifier.iprsType | 특허 | - |
dc.identifier.patentApplicationNumber | 14614884 | - |
dc.identifier.patentRegistrationNumber | 9484924 | - |
dc.date.application | 2015-02-05 | - |
dc.date.registration | 2016-11-01 | - |
dc.publisher.country | US | - |
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