Rank-Level Parallelism in DRAM

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DRAM systems are hierarchically organized: Channel-Rank-Bank. A channel is connected to multiple ranks, and each rank has multiple banks. This hierarchical structure facilitates creating parallelisms in DRAM. The current DRAM architecture supports bank-level parallelism; as many rows as banks can be moved simultaneously at bank-level. However, rank-level parallelism is not supported. For this reason, only one column can be accessed at a time, although each rank has its own data bus that can carry a column. Namely, current DRAM operations do not exploit the structural opportunity created by multiple ranks. We, therefore, propose a novel DRAM architecture supporting rank-level parallelism. Thereby, as many columns as ranks can be moved concurrently at rank-level. In this paper, we illustrate the rank-level parallelism and its benefit in DRAM operations.
Publisher
IEEE COMPUTER SOC
Issue Date
2017-07
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON COMPUTERS, v.66, no.7, pp.1274 - 1280

ISSN
0018-9340
DOI
10.1109/TC.2017.2654339
URI
http://hdl.handle.net/10203/224773
Appears in Collection
EE-Journal Papers(저널논문)
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