DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shin, Wongyu | ko |
dc.contributor.author | Jang, Jaemin | ko |
dc.contributor.author | Choi, Jungwhan | ko |
dc.contributor.author | Suh, Jinwoong | ko |
dc.contributor.author | Kwon, Yongkee | ko |
dc.contributor.author | Moon, Youngsuk | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2017-07-18T05:42:18Z | - |
dc.date.available | 2017-07-18T05:42:18Z | - |
dc.date.created | 2017-07-03 | - |
dc.date.created | 2017-07-03 | - |
dc.date.created | 2017-07-03 | - |
dc.date.created | 2017-07-03 | - |
dc.date.issued | 2017-07 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPUTERS, v.66, no.7, pp.1274 - 1280 | - |
dc.identifier.issn | 0018-9340 | - |
dc.identifier.uri | http://hdl.handle.net/10203/224773 | - |
dc.description.abstract | DRAM systems are hierarchically organized: Channel-Rank-Bank. A channel is connected to multiple ranks, and each rank has multiple banks. This hierarchical structure facilitates creating parallelisms in DRAM. The current DRAM architecture supports bank-level parallelism; as many rows as banks can be moved simultaneously at bank-level. However, rank-level parallelism is not supported. For this reason, only one column can be accessed at a time, although each rank has its own data bus that can carry a column. Namely, current DRAM operations do not exploit the structural opportunity created by multiple ranks. We, therefore, propose a novel DRAM architecture supporting rank-level parallelism. Thereby, as many columns as ranks can be moved concurrently at rank-level. In this paper, we illustrate the rank-level parallelism and its benefit in DRAM operations. | - |
dc.language | English | - |
dc.publisher | IEEE COMPUTER SOC | - |
dc.title | Rank-Level Parallelism in DRAM | - |
dc.type | Article | - |
dc.identifier.wosid | 000403288900016 | - |
dc.identifier.scopusid | 2-s2.0-85025651372 | - |
dc.type.rims | ART | - |
dc.citation.volume | 66 | - |
dc.citation.issue | 7 | - |
dc.citation.beginningpage | 1274 | - |
dc.citation.endingpage | 1280 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPUTERS | - |
dc.identifier.doi | 10.1109/TC.2017.2654339 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.contributor.nonIdAuthor | Suh, Jinwoong | - |
dc.contributor.nonIdAuthor | Kwon, Yongkee | - |
dc.contributor.nonIdAuthor | Moon, Youngsuk | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | DRAM | - |
dc.subject.keywordAuthor | main memory | - |
dc.subject.keywordAuthor | MiB | - |
dc.subject.keywordAuthor | middle buffer | - |
dc.subject.keywordAuthor | mRLP | - |
dc.subject.keywordAuthor | rank-level parallelism | - |
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