A 15 mu m-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory

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This paper presents a narrow-pitch readout circuit for multi-level phase change memory (PCM) employing an architecture of two-step 5 bit logarithmic ADC. A single-slope-architecture based fine ADC yields a 15 mu m-width compact single channel readout circuit for column parallel readout structure. A current-mode 2 bit flash ADC for coarse conversion and the pipelined architecture between the coarse and fine conversion enhance the readout rate up to 13 Mcells/sec. With the enhanced residue accuracy provided by the replica circuit of residue generator, the ADC achieves excellent linearity of 9.96 b (linear ADC equivalent). The integration-based residue generation effectively reduces circuit noise and yields 8.7 ENOB. The prototype chip was fabricated in a 65 nm CMOS process and the measured power consumption from a single channel readout circuit was 105 pW at 13 Mcells/sec conversion rate at 1.2 V supply.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2015-10
Language
English
Article Type
Article; Proceedings Paper
Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.10, pp.2431 - 2440

ISSN
0018-9200
DOI
10.1109/JSSC.2015.2453236
URI
http://hdl.handle.net/10203/205266
Appears in Collection
EE-Journal Papers(저널논문)
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