DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jin, Dong-Hwan | ko |
dc.contributor.author | Kwon, Ji-Wook | ko |
dc.contributor.author | Kim, Hyeon-June | ko |
dc.contributor.author | Hwang, Sun-Il | ko |
dc.contributor.author | Shin, Mincheol | ko |
dc.contributor.author | Cheon, Junho | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2016-04-20T06:20:13Z | - |
dc.date.available | 2016-04-20T06:20:13Z | - |
dc.date.created | 2015-11-02 | - |
dc.date.created | 2015-11-02 | - |
dc.date.created | 2015-11-02 | - |
dc.date.created | 2015-11-02 | - |
dc.date.issued | 2015-10 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.10, pp.2431 - 2440 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/205266 | - |
dc.description.abstract | This paper presents a narrow-pitch readout circuit for multi-level phase change memory (PCM) employing an architecture of two-step 5 bit logarithmic ADC. A single-slope-architecture based fine ADC yields a 15 mu m-width compact single channel readout circuit for column parallel readout structure. A current-mode 2 bit flash ADC for coarse conversion and the pipelined architecture between the coarse and fine conversion enhance the readout rate up to 13 Mcells/sec. With the enhanced residue accuracy provided by the replica circuit of residue generator, the ADC achieves excellent linearity of 9.96 b (linear ADC equivalent). The integration-based residue generation effectively reduces circuit noise and yields 8.7 ENOB. The prototype chip was fabricated in a 65 nm CMOS process and the measured power consumption from a single channel readout circuit was 105 pW at 13 Mcells/sec conversion rate at 1.2 V supply. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 15 mu m-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory | - |
dc.type | Article | - |
dc.identifier.wosid | 000362359700018 | - |
dc.identifier.scopusid | 2-s2.0-85027953514 | - |
dc.type.rims | ART | - |
dc.citation.volume | 50 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 2431 | - |
dc.citation.endingpage | 2440 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2015.2453236 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.contributor.nonIdAuthor | Kim, Hyeon-June | - |
dc.contributor.nonIdAuthor | Shin, Mincheol | - |
dc.contributor.nonIdAuthor | Cheon, Junho | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | Logarithmic ADC | - |
dc.subject.keywordAuthor | multi-level cell memory | - |
dc.subject.keywordAuthor | phase change random access memory | - |
dc.subject.keywordAuthor | resistance readout circuit | - |
dc.subject.keywordAuthor | two-step ADC | - |
dc.subject.keywordPlus | ADC | - |
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