Influence of gate dielectric/channel interface engineering on the stability of amorphous indium gallium zinc oxide thin-film transistors

Abstract

We report the simultaneous improvements of the threshold voltage (V-th) stabilities under the prolonged positive gate bias stress (PBS) and negative gate bias under illumination stress (NBIS) by employing the gate dielectric/channel interface engineering in the bottom-gate, DC-sputtered amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFT). In the interfacial region, a-IGZO is grown under the low oxygen partial pressure (P-O2) condition to minimize the damage from highly energetic oxygen anion bombardment into the substrate during sputtering. Meanwhile, high P-O2 is employed during the bulk growth of active film to reduce the oxygen vacancy (V-O) related defects in a-IGZO, which is known to be a main cause for the degradation of the electrical properties of TFT under NBIS. Owing to the lower damage of the gate dielectric by interface engineering during sputter deposition, the charge trapping or injection probability into the gate dielectric is diminished. Consequently, Vth instabilities due to both the electron trapping under PBS and the trapping of positively charged species under NBIS are alleviated simultaneously.