Single-step glitch-free NAND-based digitally controlled delay lines using dual loops

Abstract

To remove glitches occurring in NAND-based digitally controlled delay lines (DCDLs), a novel glitch-free architecture is presented. Compared with the previous structures requiring multiple control steps, the proposed DCDL employs a self-delayed inner loop to remove all the glitches by applying a single-step control-code switching, reducing the control complexity remarkably without increasing the minimum delay as well as the resolution.