DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Youngjoo | ko |
dc.contributor.author | Park, In-Cheol | ko |
dc.date.accessioned | 2014-09-01T08:39:30Z | - |
dc.date.available | 2014-09-01T08:39:30Z | - |
dc.date.created | 2014-07-08 | - |
dc.date.created | 2014-07-08 | - |
dc.date.issued | 2014-06 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v.50, no.13, pp.930 - 931 | - |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/189644 | - |
dc.description.abstract | To remove glitches occurring in NAND-based digitally controlled delay lines (DCDLs), a novel glitch-free architecture is presented. Compared with the previous structures requiring multiple control steps, the proposed DCDL employs a self-delayed inner loop to remove all the glitches by applying a single-step control-code switching, reducing the control complexity remarkably without increasing the minimum delay as well as the resolution. | - |
dc.language | English | - |
dc.publisher | INST ENGINEERING TECHNOLOGY-IET | - |
dc.title | Single-step glitch-free NAND-based digitally controlled delay lines using dual loops | - |
dc.type | Article | - |
dc.identifier.wosid | 000337914900017 | - |
dc.identifier.scopusid | 2-s2.0-84902660846 | - |
dc.type.rims | ART | - |
dc.citation.volume | 50 | - |
dc.citation.issue | 13 | - |
dc.citation.beginningpage | 930 | - |
dc.citation.endingpage | 931 | - |
dc.citation.publicationname | ELECTRONICS LETTERS | - |
dc.identifier.doi | 10.1049/el.2014.0331 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Park, In-Cheol | - |
dc.type.journalArticle | Article | - |
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