A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation
- Publisher
- IEEE
- Issue Date
- 2011-05-15
- Language
- English
- Citation
2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, pp.430 - 433
- ISSN
- 0271-4310
- Appears in Collection
- EE-Conference Papers(학술회의논문)
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