A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, W.-Y. | ko |
| dc.contributor.author | Kim, Lee-Sup | ko |
| dc.date.accessioned | 2013-03-28T09:03:07Z | - |
| dc.date.available | 2013-03-28T09:03:07Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2011-05-15 | - |
| dc.identifier.citation | 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, pp.430 - 433 | - |
| dc.identifier.issn | 0271-4310 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/164348 | - |
| dc.language | English | - |
| dc.publisher | IEEE | - |
| dc.title | A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000297265300104 | - |
| dc.identifier.scopusid | 2-s2.0-79960876363 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 430 | - |
| dc.citation.endingpage | 433 | - |
| dc.citation.publicationname | 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 | - |
| dc.identifier.conferencecountry | BL | - |
| dc.identifier.conferencelocation | Rio de Janeiro | - |
| dc.contributor.localauthor | Kim, Lee-Sup | - |
| dc.contributor.nonIdAuthor | Lee, W.-Y. | - |
- Appears in Collection
- EE-Conference Papers(학술회의논문)
- Files in This Item
- There are no files associated with this item.
This item is cited by other documents in WoS
| ⊙ Detail Information in WoSⓡ | Click to see |  |
| ⊙ Cited 2 items in WoS | Click to see citing articles in |  |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.