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Scheduling algorithm for partially parallel architecture of ldpc decoder by matrix permutation

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Park, In-Cheolresearcher / Kang, SH
Publisher
IEEE
Issue Date
2005-05-23
Language
English
Citation

IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, pp.5778 - 5781

ISSN
0271-4310
URI
http://hdl.handle.net/10203/1558
Appears in Collection
EE-Conference Papers(학술회의논문)
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