Scheduling algorithm for partially parallel architecture of ldpc decoder by matrix permutation
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Park, In-Cheol | ko |
| dc.contributor.author | Kang, SH | ko |
| dc.date.accessioned | 2007-09-21T03:00:11Z | - |
| dc.date.available | 2007-09-21T03:00:11Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2005-05-23 | - |
| dc.identifier.citation | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, pp.5778 - 5781 | - |
| dc.identifier.issn | 0271-4310 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/1558 | - |
| dc.language | English | - |
| dc.language.iso | en_US | en |
| dc.publisher | IEEE | - |
| dc.title | Scheduling algorithm for partially parallel architecture of ldpc decoder by matrix permutation | - |
| dc.type | Conference | - |
| dc.identifier.wosid | 000232002405107 | - |
| dc.identifier.scopusid | 2-s2.0-33750918495 | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 5778 | - |
| dc.citation.endingpage | 5781 | - |
| dc.citation.publicationname | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 | - |
| dc.identifier.conferencecountry | JA | - |
| dc.identifier.conferencelocation | Kobe | - |
| dc.embargo.liftdate | 9999-12-31 | - |
| dc.embargo.terms | 9999-12-31 | - |
| dc.contributor.localauthor | Park, In-Cheol | - |
| dc.contributor.nonIdAuthor | Kang, SH | - |
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