Investigation of Isolation-Dielectric Effects of PDSOI FinFET on Capacitorless 1T-DRAM

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The isolation-dielectric effects of a FinFET structure with a partially depleted (PD) silicon-on-insulator (PDSOI) region as a charge storage node on the characteristics of 1T-DRAM are reported in this brief. By introducing the low-permittivity isolation dielectric as an isolation layer among the active regions, the body potential over the PDSOI region is reduced due to the decreased capacitive coupling between the gate and the PD region; hence, it yields a widened 1T-DRAM sensing margin despite high OFF-state and low ON-state currents. The increased gate height shows the high sensitivity of the sensing margin through the isolation-dielectric permittivity in the PDSOI FinFET 1T-DRAM.
Publisher
IEEE-Inst Electrical Electronics Engineers Inc
Issue Date
2009-12
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON ELECTRON DEVICES, v.56, no.12, pp.3232 - 3235

ISSN
0018-9383
DOI
10.1109/TED.2009.2033412
URI
http://hdl.handle.net/10203/100844
Appears in Collection
EE-Journal Papers(저널논문)
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