Investigation of Isolation-Dielectric Effects of PDSOI FinFET on Capacitorless 1T-DRAM

Abstract

The isolation-dielectric effects of a FinFET structure with a partially depleted (PD) silicon-on-insulator (PDSOI) region as a charge storage node on the characteristics of 1T-DRAM are reported in this brief. By introducing the low-permittivity isolation dielectric as an isolation layer among the active regions, the body potential over the PDSOI region is reduced due to the decreased capacitive coupling between the gate and the PD region; hence, it yields a widened 1T-DRAM sensing margin despite high OFF-state and low ON-state currents. The increased gate height shows the high sensitivity of the sensing margin through the isolation-dielectric permittivity in the PDSOI FinFET 1T-DRAM.