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Showing results 44461 to 44480 of 279183
| Chip calorimeters for cellular metabolic rate measurements and cell-based assay Lee, Wonhee, IEEE nanomed 2018, IEEE, 2018-12-05 |
| Chip Crack Imaging Detection Based on Line Laser Phase-Locked Thermal Imaging Ying, Xu; Wang Qingyuan; Luo Congcong; Sohn, Hoon, LASER & OPTOELECTRONICS PROGRESS, v.57, no.6, 2020-03 |
| Chip package hybrid I/O clock distribution for 2Gbps DDR graphic memory = 2기가 bps급 DDR 그래픽 메모리를 위한 칩 패키지 하이브리드 I/O클럭 분배에 관한 연구link Ryu, Chung-Hyun; 류충현; et al, 한국과학기술원, 2004 |
| Chip scale package for SAW filter on the oxidized porous silicon using flip-chip bonding and Cu plated metal wall Ha M.-L.; Lee J.-S.; Kwon, Young Se, 52nd Electronic Components and Technology Conference, pp.372 - 377, Electronic Components and Technology Conference, 2002-05-28 |
| Chip warpage damage model for ACA film type electronic packages Yang, SY; Kwon, WS; Lee, Soon-Bok; Paik, Kyung-Wook, ADVANCES IN FRACTURE AND STRENGTH, PTS 1- 4 BOOK SERIES: KEY ENGINEERING MATERIALS, v.297-300, no.2, pp.1 - 4, 2005 |
| Chip warpage damage model for ACA/NCA film type electronic packages Lee, Soon-Bok; Yang, Se Young; Kwon, Woon-Seong; Paik, Kyoung-Wook, APCFS(Asian Pacific Conf for Fracture and Strength)'04, pp.103 - 103, 2004 |
| Chip warpage model for reliability prediction of delamination failures Yang, Se Young; Kwon, Woon-Seong; Lee, Soon-Bok, MICROELECTRONICS RELIABILITY, v.52, no.4, pp.718 - 724, 2012-04 |
| Chip-based analysis of SUMO (small ubiquitin-like modifier) conjugation to a target protein Oh, Young-Hee; Hong, Mi-Young; Jin, Zongwen; Lee, Tae-Ryong; Han, Min-Kyu; Park, Sun-Young; Kim, Hak-Sung, BIOSENSORS & BIOELECTRONICS, v.22, no.7, pp.1260 - 1267, 2007-02 |
| Chip-based energy transfer system between quantum dots and gold nanoparticles for analysis of protein glycosylation Kim, YP; Park, S; Oh, E; Oh, YH; Kim, Hak-Sung, 2008 NSTI Nanotechnology Conference and Trade Show, NSTI Nanotech 2008 Joint Meeting, Nanotechnology 2008, pp.244 - 247, 2008-06-01 |
| Chip-based microenzyme assay for kinase using antibody Lee, S.J; Lee, SangYup, ChungNam-Kyushu International Symposium, ChungNam-Kyushu International Symposium, 2002-12-06 |
| Chip-based microenzyme assay for kinase using antibody Lee, SangYup, Center for Ultramicrochemical Process Systems Workshop, Center for Ultramicrochemical Process Systems Workshop, 2003-01-17 |
| Chip-based protease assay using fluorescence resonance energy transfer between quantum dots and fluorophores Kim, Young Pil; Oh, Young-Hee; Oh, Eunkeu; Kim, Hak-Sung, BIOCHIP JOURNAL, v.1, no.4, pp.228 - 233, 2007-12 |
| Chip-in packaging technology using aluminum substrate (pocket embedded packaging) = 알루미늄 기판을 이용한 Chip-In Packaging 기술link Kim, Kyoung-Min; 김경민; et al, 한국과학기술원, 2008 |
| Chip-level 2-D RAKE receiver with symbol-level searcher beamforming Chang K.H.; Sohn I.S.; Chang K.S., IEEE VTS 50th Vehicular Technology Conference, VTC 1999-Fall, v.50, pp.924 - 928, 1999-09-19 |
| Chip-Level Simultaneous Switching Current Measurement in Power Distribution Network Using Magnetically Coupled Embedded Current Probing Structure Kim, Jonghoon J.; Cho, Changhyun; Bae, Bumhee; Kim, Suk Jin; Kong, Sunkyu; Kim, Hee-Gon; Jung, Daniel Hyunsuk; et al, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.4, no.12, pp.1963 - 1972, 2014-12 |
| Chip-level Wireless Power Transfer Scheme Design for Next Generation Wireless Interconnected Three-Dimensional Integrated Circuits Song, Jinwook; Jung, Seungtaek; Park, Shinyoung; Kim, Jonghoon; Hong, Seokwoo; Kim, Joungho, IEEE Wireless Power Transfer Conference (WPTC), IEEE Wireless Power Transfer Conference 2017, 2017-05-10 |
| Chip-level wireless power transfer scheme design using magnetic-field resonant coupling for next generation wireless interconnected 3-D IC = 차세대 무선 삼차원 반도체를 위한 자기장 공명 기술을 이용한 칩-단위 무선 전력 전송 도식 설계link Song, Jinwook; Kim, Joung Ho; et al, 한국과학기술원, 2018 |
| Chip-package co-design of power distribution network for system-in-package applications Kim, G.; Kam, D.G.; Chung, D.; Kim, Joungho, 6th Electronics Packaging Technology Conference, EPTC 2004, pp.499 - 501, IEEE, 2005-12-08 |
| Chip-package co-modeling & verification of noise coupling & generation in CMOS DC/DC buck converter Song, T.; Kim, J.; Pak, J.; Kim, Joungho, 20th International Zurich Symposium on Electromagnetic Compatibility, EMC Zurich 2009, pp.285 - 288, IEEE, 2009-01-12 |
| Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method Kim, Jae-Min; Lee, Woo-Jin; Shim, Yu-Jeong; Shim, Jong-Joo; Kim, Ki-Yeong; Pak, Jun-So; Kim, Joung-Ho, IEEE TRANSACTIONS ON ADVANCED PACKAGING, v.33, no.3, pp.647 - 659, 2010-08 |
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