Hybrid schemes and variable-size subblock TLBs: Aggressive superpage supports

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While superpages are an efficient solution to increase TLB reach, strong contraint for using superpages hinders the actual utilization. Two previous solutions, a partial-subblock TLB and the shadow memory were proposed to loose the contraint. A partial-subblock TLB looses only a small portion of the contraint and limits the superpage size at a cost. The shadow memory looses most of the constraint but introduces other serious problems. We propose three novel approaches to improve superpage supports. First, we propose a hybrid scheme which integrates both the shadow memory and a partial-subblock TLB, thereby enjoying the benefits inherited from both sides. The hybrid scheme has as high a superpage utilization as the shadow memory, and avoids most of the problems in the shadow memory by the virtue of partial-subblock TLB. Second, VS-TLBs are an extension of subblock TLBs to support multiple page subblocks, while subblock TLBs can support only single page subblocks. VS-TLBs have a much larger TLB reach than subblock TLBs with a cost of a small number of bits. Last, we propose VS-hybrid which replaces the partial-subblock TLB in the hybrid scheme with a partial VS-TLB. It supports multiple page subblocks in the hybrid scheme. Therefore, it takes both advantages of the hybrid scheme and the expanded subblock size. The simulation results show that the proposed schemes take a large amount of performance gain in the benchmark application programs.
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Issue Date
2002-10
Language
English
Article Type
Article
Keywords

PROCESSORS; MEMORIES

Citation

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E85D, no.10, pp.1609 - 1618

ISSN
0916-8532
URI
http://hdl.handle.net/10203/86020
Appears in Collection
RIMS Journal Papers
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