The isochronal annealing study on the bias stressed amorphous silicon thin film transistors

Abstract

The annealing behavior of bias stressed hydrogenated amorphous silicon thin film transistors is studied using the isochronal annealing method. It is observed that the annealing behavior is changed according to the degradation conditions. The isochronal annealing spectra can be decomposed into three annealing peaks (high temperature, intermediate temperature and low temperature peaks). The high temperature peaks and the low temperature peaks are attributed to defect annealing and charge detrapping, respectively. As an origin of the intermediate temperature peaks it is proposed that detrapping of the deeply trapped charges and annealing of the defects in the interface between the undoped amorphous silicon layer and the silicon nitride layer occurs.