Modified delta sigma modulator for low phase noise frequency synthesizer = 저 위상 잡음 주파수 합성기를 위한 변형 델타 시그마 변조기

The demand for wireless system products has been increasing rapidly due to the success of handheld communication device and the convergence trend. The local oscillator of the wireless system is usually implemented as a phase locked loop (PLL) to get a better phase noise performance. As wireless standards are getting evolved, the phase noise specifications also are getting harder, because the system performance such as BER and SNR can be affected by it. Therefore, the frequency synthesizer, or LO, used in wireless system should have the phase noise specification as low as possible. However, the phase noise performance is varied depending on the input of delta-sigma modulator and it should be suppressed for low phase noise specification. The main idea of the proposed DSM is to change from original delta-sigma modulator input to the delta-sigma modulator input value that has better noise shaping. The output phase noise performance has lower in band phase noise and larger out band phase noise when the input is applied toward 0.5 because the DSM output is PWM encoded. Thus, if the input of the DSM is concentrated on the around 0.5, the DSM in-band phase noise is better. The maximum in-band phase noise difference between the proposed architecture and the conventional architecture is about -240 dBc/Hz. It could be concluded that the in-band DSM phase noise performance is improved by using the proposed DSM architecture. Thus, it indicates that the CP noise is always dominant within the in-band. With CP noise, the in-band phase noise performance is improved by -10 dBc/Hz. Although the proposed architecture is implemented with the $2^{nd}$ order DSM, the proposed architecture can be adopted to the DSM of any order. This could be an advantage because the backward compatibility is very high. The characteristics of the frequency synthesizer based on the proposed delta-sigma modulator are given in the followings. The frequency synthesizer shows lock-i...
Advisors
Park, In-Cheolresearcher박인철researcher
Publisher
한국과학기술원
Issue Date
2009
Identifier
308829/325007  / 020073329
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2009.2, [ vii, 58 p. ]

Keywords

Phase Locked Loop; Frequency Synthesizer; Delta Sigma Modulator; Phase Noise; 위상 동기 루프; 주파수 합성기; 델타 시그마 변조기; 위상 잡음; Phase Locked Loop; Frequency Synthesizer; Delta Sigma Modulator; Phase Noise; 위상 동기 루프; 주파수 합성기; 델타 시그마 변조기; 위상 잡음

URI
http://hdl.handle.net/10203/38709
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=308829&flag=t
Appears in Collection
EE-Theses_Master(석사논문)
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