Design of low power digital hearing aid chip = 저전력 디지털 보청기 칩의 설계

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The hearing problem has become more and more serious. As a result, needs for hearing aids have been increased. One of the most important measure of performance of a hearing aid is its power. And to compensate the different hearing losses of each person, digital hearing aids are required. In this work, a single mixed-signal chip for a digital hearing aid instrument is designed in low threshold 0.18um CMOS process. This chip comprises the following functions: a microphone preamplifier with MOS Resistive Circuit (MRC), a 1-bit 2nd order delta-sigma AD converter, a programmable 2 channel digital signal processor (DSP) with a ROM and serial interface, a 1-bit 2nd order delta-sigma DA converter, a H-bridge and a ring oscillator. Supply voltage is determined to be 1V to prevent unnecessary power consumption. Total power consumption for a full swing input signal is 275uW. This enables at least 2 weeks of life time of hearing aids at 16 hours/day for a small zinc-air battery. The typical SNR and THD of the complete signal path are 72dB and -45dB, each.
Advisors
Yoo, Hoi-Junresearcher유회준researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2004
Identifier
238418/325007  / 020023153
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2004.2, [ iii, 58 p. ]

Keywords

DIGITAL SIGNAL PROCESSOR; DIGITAL; LOW POWER; HEARING AID; CMOS; CMOS; 디지털 신호 처리기; 디지털; 저전력; 보청기

URI
http://hdl.handle.net/10203/37741
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=238418&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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