Energy-efficient real-time object recognition processor with visual attention engine = 시각집중 가속기를 집적한 에너지 효율적인 실시간 물체 인식 프로세서

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As object recognition requires huge computation power to deal with complex image processing tasks, it is very challenging to meet real-time processing demands under low-power constraints for embedded systems. In this thesis, an energy-efficient real-time object recognition processor is designed and implemented with bio-inspired visual attention engine. This thesis presents various aspects for the object recognition processor from algorithm, architecture to the system demonstration. Bio-inspired attention-based object recognition algorithm is devised to reduce computational complexity of the object recognition. The object recognition processor contains an ARM10-compatible 32-bit main processor, 8 SIMD PE clusters with 8 processing elements in each cluster, a cellular neural network based visual attention engine (VAE), a matching accelerator, and a DMA-like external interface. The proposed processor has three key features to optimize energy efficiency of the object recognition processor: attention-based object recognition SoC with the VAE, a configurable SIMD/MIMD dual-mode parallelism, and a low-latency application-specific NoC. The VAE with 2-D shift register array is utilized to accelerate visual attention algorithm for selecting salient image regions rapidly. The dual-mode parallel processor is configured into SIMD or MIMD modes to perform data-intensive image processing operations within only the pre-selected attention regions while exploiting pixel-level and object-level parallelisms required for the attention-based object recognition. The low-latency NoC employs dual channel, adaptive switching and packet-based power management, providing 76.8 GB/s aggregated bandwidth. The performance analysis results using a cycle-accurate architecture simulator show the proposed architecture improves the energy efficiency by 69\% and recognition speed by 38\% over the previous implementation. The chip, fabricated in a 0.13 μm 1P 8M CMOS process, takes die size of $36 ...
Yoo, Hoi-Junresearcher유회준researcher
한국과학기술원 : 전기및전자공학전공,
Issue Date
327767/325007  / 020065019

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2009. 8., [ 109 p. ]


Object Recognition; Visual Attention Engine; Multi-Core; Network-on-Chip; 물체인식; 시각집중 가속기; 다중코어; 네트워크 온칩; Object Recognition; Visual Attention Engine; Multi-Core; Network-on-Chip; 물체인식; 시각집중 가속기; 다중코어; 네트워크 온칩

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