Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems

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This letter presents a new multi-bit flipping decoding algorithm for low-density parity-check codes, which can enhance hard-information-based decoding performance for NAND storage systems. Since the conventional enhancement techniques developed for bit-flipping decoding require soft information, the long latency taken to generate the soft information, makes it hard to apply them to practical NAND storage systems. The proposed algorithm requires only hard information and achieves the better performance than previous hard-informationbased algorithms. The proposed method flips multiple bits in each iteration, but the maximum number of bits to be flipped in an iteration is restricted to prevent overcorrection. To relax the hardware complexity of sorting, in addition, an efficient approximation method is proposed, reducing the hardware complexity of a 512-input sorter by 48.3% without degrading the performance noticeably.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-05
Language
English
Article Type
Article
Keywords

PARITY-CHECK CODES; DECISION ERROR-CORRECTION; FLASH MEMORY; ALGORITHMS

Citation

IEEE COMMUNICATIONS LETTERS, v.21, no.5, pp.979 - 982

ISSN
1089-7798
DOI
10.1109/LCOMM.2017.2656119
URI
http://hdl.handle.net/10203/224089
Appears in Collection
EE-Journal Papers(저널논문)
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