Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems

Abstract

This letter presents a new multi-bit flipping decoding algorithm for low-density parity-check codes, which can enhance hard-information-based decoding performance for NAND storage systems. Since the conventional enhancement techniques developed for bit-flipping decoding require soft information, the long latency taken to generate the soft information, makes it hard to apply them to practical NAND storage systems. The proposed algorithm requires only hard information and achieves the better performance than previous hard-informationbased algorithms. The proposed method flips multiple bits in each iteration, but the maximum number of bits to be flipped in an iteration is restricted to prevent overcorrection. To relax the hardware complexity of sorting, in addition, an efficient approximation method is proposed, reducing the hardware complexity of a 512-input sorter by 48.3% without degrading the performance noticeably.