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Showing results 3001 to 3020 of 275953
| A 10 Bits Modified VCC Interpolation and DVO Correction by Drain Current Injection Lee, Sungwoo; Kim, Ki-Duk; Park, Kyu-Sung; Park, Chang-Byung; Lee, Byung-Hun; Jeon, Jin-Yong; Jung, Seung-Chul; et al, 2010 SID Symposium, pp.58 - 61, Wiley, 2010-05 |
| A 10 Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption with Direct Feedback Method Kim, Yong-Hun; Lee, Dongil; Lee, Daewoong; Kim, Lee-Sup, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.11, pp.1539 - 1543, 2018-11 |
| A 10 Gbps Optical Receiver Analog Front-End and MZM Driver in 65nm CMOS Qahir, Abdul; Lee, Sang-Gug, IDEC Journal of Integrated Circuits and Systems, v.9, no.2, pp.14 - 19, 2023-04 |
| A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section Kim, Jong Pal; Lee, Wonseok; Suh, Junyeub; Lee, Hyungwoo; Lee, Kyuil; Ahn, Ho Young; Seo, Min-Jae; et al, 42nd Annual International Conference of the IEEE-Engineering-in-Medicine-and-Biology-Society (EMBC), pp.4012 - 4015, IEEE, 2020-07 |
| A 10-B 20-MSAMPLE/S LOW-POWER CMOS ADC SONG, WC; Choi, HaeWook; KWAK, SU; SONG, BS, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.30, no.5, pp.514 - 521, 1995-05 |
| A 10-bit 300Msample/s pipelined ADC using time-interleaved SAR ADC for front-end stages Kim, Y.-H.; Lee, J.; Cho, SeongHwan, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, pp.4041 - 4044, IEEE, 2010-05-30 |
| A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications Oh, Ghilgeun; Lee, Chang-Kyo; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.61, no.1, pp.6 - 10, 2014-01 |
| A 10-bit 50-MS/s pipelined ADC with opamp cuffent reuse Ryu, Seung-Tak; Song, BS; Bacrania, K, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.42, pp.475 - 485, 2007-03 |
| A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS Chung, Hayun; Ishikuro, Hiroki; Kuroda, Tadahiro, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.47, no.5, pp.1232 - 1241, 2012-05 |
| A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs Kim, Hyun Sik; Yang, Jun-Hyeok; Park, Sang Hui; Ryu, Seung-Tak; Cho, Gyu-Hyeong, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.3, pp.766 - 782, 2014-03 |
| A 10-bit Modified VCC Interpolation and DVO Correction Using Drain-Current Injection Cho, Gyu-Hyeong; Lee, SW; Park, GS; Kim, KD; Park, CB; Lee, BH; Jeon, JY; et al, SID 10 DIGEST, pp.58 - 61, SID 10 DIGEST, 2010-05-28 |
| A 10-bit Serial Integration-Type DAC Architecture for AMLCD Column Drivers Cho, Gyu-Hyeong; Kim, Ki-Duk; Woo, Young-Jin; Lee, Sung-Woo; Jeon, Yong-Joon; Jeon, Jin-Yong; Yang, Jun-Hyeok; et al, SID International Symposium, pp.379 - 382, 2009 |
| A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS Chung, Sang-Hye; Kim, Young Ju; Kim, Yonghun; Kim, Lee-Sup, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.63, no.3, pp.264 - 268, 2016-03 |
| A 10-Gb/s CDR with an adaptive optimum loop-bandwidth calibrator for serial communication links Lee, Joon Yeong; Yoon, Jonghyeok; Bae, Hyeon-Min, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.61, no.8, 2014-08 |
| A 10-node tetrahedral element with condensed Lagrange multipliers for the modified couple stress theory Choi, Jae-Hoon; Lee, Byung-Chai; Sim, Gi-Dong, COMPUTERS & STRUCTURES, v.246, pp.106476, 2021-04 |
| A 10-Phase 270MHz 5000ppm spread spectrum clock generator Lee, W.-Y.; Kim, Lee-Sup, 2008 International SoC Design Conference, ISOCC 2008, 2008-11-24 |
| A 10-uW digital signal processor with adaptive-SNR monitoring for a sub-1V digital hearing aid Yoo, J.; Kim, S.; Cho, N.; Song, S.-J.; Yoo, Hoi-Jun, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, pp.3361 - 3364, 2006-05-21 |
| A 10-µs-tuning MEMS-actuated Gires-Tournois filter for use as a tunable wavelength demultiplexer and a tunable OCDMA encoder/decoder Ebrahimi, Paniz; Kargar, Mahyar; Hauer, Michelle C.; Willner, Alan E.; Yu, Kyoungsik; Solgaard , Olav, OFC(Optical Fiber Communication Conference) , OFC, 2004 |
| A 10.1 '' 183-mu W/electrode, 0.73-mm(2)/sensor High-SNR 3-D Hover Sensor Based on Enhanced Signal Refining and Fine Error Calibrating Techniques Huh, Yeunhee; Hong, Sung-Wan; Park, Sanghui; Shin, Changsik; Bang, Jun-Suk; Park, Changbyung; Park, Sungsoo; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.4, pp.1079 - 1088, 2018-04 |
| A 10.1" 56-channel, 183 uW/electrode, 0.73 mm2/sensor high SNR 3D hover sensor based on enhanced signal refining and fine error calibrating techniques Huh, Yeunhee; Hong, Sung-Wan; Park, Sang-Hui; Bang, Jun-Suk; Park, Changbyung; Park, Sungsoo; Gwon, Hui-Dong; et al, 31st Symposium on VLSI Circuits, pp.C308 - C309, IEEE, 2017-06 |
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