A 10-B 20-MSAMPLE/S LOW-POWER CMOS ADC

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A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unsealed pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines, Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation, The ADC implemented using a double-poly 1.2 mu m CMOS technology exhibits a DNL of +/-0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz, The chip die area is 13 mm(2).
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
1995-05
Language
English
Article Type
Article
Keywords

PARALLEL A/D CONVERTER; CONVERSION; S/H

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.30, no.5, pp.514 - 521

ISSN
0018-9200
URI
http://hdl.handle.net/10203/67671
Appears in Collection
EE-Journal Papers(저널논문)
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