DC Field | Value | Language |
---|---|---|
dc.contributor.author | SONG, WC | ko |
dc.contributor.author | Choi, HaeWook | ko |
dc.contributor.author | KWAK, SU | ko |
dc.contributor.author | SONG, BS | ko |
dc.date.accessioned | 2013-02-27T09:09:09Z | - |
dc.date.available | 2013-02-27T09:09:09Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1995-05 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.30, no.5, pp.514 - 521 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/67671 | - |
dc.description.abstract | A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unsealed pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines, Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation, The ADC implemented using a double-poly 1.2 mu m CMOS technology exhibits a DNL of +/-0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz, The chip die area is 13 mm(2). | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | PARALLEL A/D CONVERTER | - |
dc.subject | CONVERSION | - |
dc.subject | S/H | - |
dc.title | A 10-B 20-MSAMPLE/S LOW-POWER CMOS ADC | - |
dc.type | Article | - |
dc.identifier.wosid | A1995QV83200001 | - |
dc.identifier.scopusid | 2-s2.0-0029304667 | - |
dc.type.rims | ART | - |
dc.citation.volume | 30 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 514 | - |
dc.citation.endingpage | 521 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.contributor.localauthor | Choi, HaeWook | - |
dc.contributor.nonIdAuthor | SONG, WC | - |
dc.contributor.nonIdAuthor | KWAK, SU | - |
dc.contributor.nonIdAuthor | SONG, BS | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordPlus | PARALLEL A/D CONVERTER | - |
dc.subject.keywordPlus | CONVERSION | - |
dc.subject.keywordPlus | S/H | - |
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