A 0.13-mu m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

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A 6 Gb/s/pin transceiver for DRAM interfaces is implemented in a 0.13-mu m CMOS process. Pseudo-differential signaling to overcome problems of conventional single-ended signaling is proposed. In a conventional single-ended signaling, the reference signal from a transmitter is generally used to reduce the common-mode noise which is induced by simultaneous switching noise (SSN). However, as supply voltage becomes low and data rate increases, the reference signal reduces the voltage and timing margin of receiver inputs. The proposed transceiver uses the pseudo-differential signaling without the reference signal and encoding schemes using the relation between neighboring data are proposed to remove the reference signal. In the receiver, transition-check circuit (TCC) is used to convert encoded data into original data before encoding. The proposed pseudo-differential signaling increases the eye-opening of 1:2 demuxed outputs of the receiver by 65 ps. The transceiver dissipates 242.5 mW and its active area is 1.0 mm x 0.3 mm.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2009-11
Language
English
Article Type
Article; Proceedings Paper
Keywords

DATA RECOVERY CIRCUIT; LOW-POWER; CLOCK; PHASE

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.44, pp.3146 - 3162

ISSN
0018-9200
URI
http://hdl.handle.net/10203/99759
Appears in Collection
EE-Journal Papers(저널논문)
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